1. Field of the Invention
The present invention relates to a bipolar-transistor type random access memory (RAM) having a redundancy configuration. More particularly, the present invention is directed to a defective address memory portion of a RAM.
2. Description of the Related Art
In a RAM device, a large number of memory cells are arranged along rows and columns. The density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. The density of defects is due to semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device.
Even if a device includes only one defective memory cell, however, the device cannot be operated normally, and therefore, must be scrapped. As a result, despite the lower ratio of defective memory cells, greater integration density means reduced manufacturing yield.
In a metal-insulator-semiconductor (MIS) RAM, in order to overcome the problem of defective memory cells, use is made of redundancy memory cells. When a defective memory cell is detected, a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell. In general, one or two redundancy memory cell rows or columns are usually provided.
In such a redundancy configuration, in order to store address information of such a defective row or column and to disable regular decoders so that the redundancy row or column is selected in response to an address of the defective row or column, a defective address memory circuit is required.
In the prior art, however, since there has been no preferable defective address memory circuit for a bipolar-transistor type RAM, there has been no bipolar-transistor type RAM having a redundancy configuration.